DC/DC converters are nowadays used in a plurality of different applications to provide a supply signal to loads connected thereto. For such purpose, the DC/DC converters are often pulse-width modulated with a selectable duty cycle modulation in response to a current drawn by the load connected to the converter. The DC/DC converter comprises a complementary driver having respective driver transistors, for instance a PMOS or an NMOS transistor connected in series. In operation, the transistors are selectively switched off or on depending on the pulse-width modulation. For a complementary digital driver having a P- and NMOS driver transistor connected in series, it is necessary that both transistors are not contemporarily in the on-state.
Consequently, a feedback network may be provided to recognize that one of the transistors is already in the off-state before switching on the other transistor of the complementary driver.
Furthermore, it is important in DC/DC converters to fix a minimum duration which lets one of the driver transistors of the complementary driver off instead of allowing the one driver transistor to decrease progressively to zero. As some analog parts inside the block of the DC/DC converter must be reset between the end of an on-pulse of one driver transistor and the beginning of the following one, a minimum off-time, i.e. a smallest possible off-time or a limitation below which it is not possible to go, is needed to accomplish these operations. On the other hand, it is desirable that the complementary driver does not stay off longer than necessary, even if this is usually a matter of a few nanoseconds. Such minimum off-time for the PMOS can have a very large spread, depending on production process as well as operating conditions.
Given the need of a disoverlap time, the conduction of the first and the second driver transistor of a complementary driver in the power stage raises a limitation, in particular a lower limit over the minimum duration of the off-pulse of the PMOS driver transistor.
It could therefore be helpful to provide a maximum duty cycle of the DC/DC converter even if the frequency of the pulse-width modulated signal is increased. It could further be helpful to provide an optimal disoverlap time in the conduction of the power stage complementary transistors to be maintained when the DC/DC converter is operated at a duty cycle slightly below the maximum achievable one.